To understand or debug a circuit it is often very useful to be able to observe the different signals in a visual way. This is the purpose of the timeline. This module allows the recording of signals in graphical form or in a table of value in a text file.
You can enter the logging module via the menu | Simulate |→| Chronogram |. It brings up the signal selection window.
The circuit below is an illustrative example for the timing module.
These are the clocks that serve as a driver for displaying signals. The simulation knows two particular clocks. One is imperative and named sysclk and another optional and secondary named clk
Note: it is imperative that a clock named sysclk appears in your circuit. It will be used as a time base by the chronogram module. It does not have to be connected to your circuit. It is in principle the fastest and is set to a duty cycle 1/1 tic.
Next: The Selection tab.